Nonlinear noise analysis of LC-tuned CMOS VCOs and extrinsic noise effects.
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Nonlinear noise analysis of LC-tuned CMOS VCOs and extrinsic noise effects.

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Published .
Written in English


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This thesis considers the noise performance of CMOS LC-VCOs. It is motivated by the challenges that the oscillator noise specification presents to designers of large mixed-mode systems. It treats this issue on a theoretical level and on a design level. On the theoretical level, this work presents an analytical method for examining the noise behaviour of fully-integrated, resonator-based VCOs. This is intended to give designers a more fundamental insight into the LC-oscillator"s noise performance without the need for an exhaustive use of the simulator. In the analysis, the oscillator is distilled to its simplest dynamic model: a nonlinear second-order stochastic differential equation. Nonlinear expressions for common oscillator topologies are derived and integrated into the second-order model. A variety of intrinsic and extrinsic noise models are included as well. Asymptotic solution methods are combined with the correlation theory to produce closed-form expressions for the phase noise. These techniques readily account for a number of important properties including: state-dependent noise, positive feedback, AM-PM conversion, large phase deviations and noise modulation. The analysis is verified in simulation with SPECTRE and experimentally with integrated VCO measurements.On the design level, this thesis considers methods of shielding oscillators from extrinsic noise. To this end, a fully-monolithic 2.4-GHz 0.18-mum CMOS LC-VCO with enhanced supply rejection is proposed and designed. Isolating the tank and switching core from the power and ground lines, the effect of supply disturbances on the VCO are reduced by 40 dB, more than a 30-dB improvement over other fully-monolithic LC-VCOs. Further, this scheme does not compromise the oscillator"s tuning sensitivity, allowing a 1-GHz (38%) tuning range. At a power dissipation of 11 mW, the measured phase noise at 100-kHz offset from a 2.9-GHz carrier is -105 dBc/Hz. Also, recognizing that typical varactor designs make LC-oscillators susceptible to common-mode disturbances a new MOS-varactor structure capable of rejecting such noise is proposed. Simulation results indicate a 5-times improvement in common-mode noise rejection for the new structure.

The Physical Object
Pagination257 leaves.
Number of Pages257
ID Numbers
Open LibraryOL20339200M
ISBN 10061291738X

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This paper presents a detailed analysis of the ultimate performance bound in simultaneously achieving low phase noise and wide tuning range in CMOS VCOs. The analysis is . A design strategy for the realization of low-phase-noise VCOs is presented. The possible realizations of integrated inductors are discussed, with emphasis on bondwire inductors. A general formula for the phase noise in LC-tuned oscillators is derived, based on the concepts of effective resistance and by: 3. 1. Introduction. The most challenging issue in the design of an integrated LC-tuned voltage-controlled oscillator (VCO) is to achieve a low-phase noise performance while keeping low-power r, the integrated inductor typically has a low quality (Q) factor due to the low resistivity of the silicon substrate and this greatly degrades the phase noise by: 9. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 2, FEBRUARY Wide-Band CMOS Low-Noise Amplifier Exploiting Thermal Noise Canceling Federico Bruccoleri, Eric A. M. Klumperink, Member, IEEE, and Bram Nauta, Senior Member, IEEE Abstract—Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source.

Full text of "Circuit Analysis Theory And Practice" See other formats. This banner text can have markup.. web; books; video; audio; software; images; Toggle navigation. [4] J. Craninckx and M. Steyaert, A GHz Low Phase Noise CMOS VCO using Optimized Hollow Inductors, IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. , May [5] J. Craninckx, Low-Phase-Noise Fully Integrated CMOS Frequency Synthesizers, Ph.D Thesis, Katholieke Universiteit Leuven, Leuven, [6] A.5/5(7). 1 Research Collection Doctoral Thesis A clock recovery circuit for 40 Gb/s using InP/InGaAs heterojunction nipolar trans.

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